||08 Settembre 2019
Postato da: AfAOne
|WinUAE 4.3.0 Beta Preview
Presto inizieranno le beta della nuova v4.3.0, queste le novità annunciate da Toni:
Future (4.3.0?) WinUAE beta series preview. Posted mainly because CPU tester changes are also included here. CPU tester posted in separate news forum thread. This thread will be unlocked later.
- Trumpcard A500AT v1.2 ROM dump found, compared to v1.1 (extracted from driver disk .driver file), main difference seems to be use of interrupts. Emulation updated. Both ROM versions have same version/date string "AT 1.1 (06 NOV 1991)", I guess they forgot to update it..
- Disk index pulses were not being generated when disk was being written (Broke Cadaver v0.1 save disk writing, has been broken at least since 3.0)
- Restoring CD32 or CDTV statefile with CD audio playing: start playing immediately, do not emulate CD audio start delays.
- Added statefile generic partial IO autoconfig board support, board is mapped in address space and visible in Hardware Info panel after restore. Each board still needs separate statefile implementation.
- CDTV audio CD playing state restore fixed.
- Don't save AGA colors chunk to statefile if config is not AGA and all AGA colors are uninitialized (if initialized: config was changed on the fly and AGA palette should be saved)
- Archos Overdrive HD (PCMCIA IDE adapter) emulation added.
- Generic PCMCIA hotswap support, each PCMCIA expansion has "PCMCIA inserted" checkbox, if ticked, card is inserted and if any other card was inserted, it gets removed first. If unticked, card is removed. Checkbox can be changed on the fly. Reason for this change is to have hotswap support that is not device type specific.
- PCMCIA SRAM and PCMCIA IDE are now expansion devices. Old PCMCIA SRAM/IDE configs need to be manually updated.
- PCMCIA conflict check was incorrect, it detected 4M Fast RAM as conflicting.
- Expansion panel selected device was unexpectedly cleared when clicking GUI elements.
- CIA overlay is unused only in Gayle based Amigas (A600, A1200) and also CD32. A4000 and A4000T models had incorrectly disabled CIA overlay emulation.
- Internal CD mount audio playback handled pregap incorrectly if previous track was in different file than current audio track and pregap was between tracks (cue/iso/wav, first audio track), it caused first 2 seconds (or length of pregap) of audio to be played with zero volume.
- High DPI support rewritten, now requires "Per Monitor DPI Aware V2" feature which was introduced in Windows 10 1703. 8.1 introduced original "V1" version which is not supported anymore. Manual GUI size/font adjustments are still supported in older Windows versions.
- GUI high DPI problems fixed, for example when moving GUI window from monitor to another monitor with different DPI usually worked very badly.
- Windowed mode bottom status bar is now high DPI compatible.
- Direct3D11 mode + Windows 10 with DXGI HDR support + HDR enabled GPU and display: use HDR compatible back buffer (DXGI_FORMAT_R16G16B16A16_FLOAT)
- Disk swapper path modifications did nothing while emulation was running.
- When overwriting configuration.backup, don't move old file to recycle bin. Backup of a backup is not that useful.
- CD32 pad emulation didn't handle weird pad reading code where pad mode selection Paula pin was in input mode and code set POTGO START bit which discharges POT caps = CD32 pad will see 0v in 3rd button line and activates CD32 pad mode.
- Enabled CD32 pad mode and normal second fire button (not CD32 blue) is pressed: override CD32 pad mode and use normal joystick mode. (This is basically same as having joystick splitter that allows to connect both CD32 pad and normal joystick at the same time)
- CIA odd address word or long read/write access returned upper and lower byte swapped.
- Switching chipset on the fly (OCS<>ECS/AGA using uae-configuration) didn't reset BEAMCON0, some other AGA only registers and sprite widths.
- Removed all 68020 cycle-exact CPU mode internal idle cycles. It wasn't good enough design (as expected), need to start from scratch later.. again.. It made real 68020 best case results too slow. (and worst case was still too fast..)
- uae-configuration didn't work in indirect UAE boot ROM mode. (uae-configuration uses C-style stack parameters and trap code didn't preserve SP)
- Added separate CPU tester project that generates test data file for configured CPU (cputestgen.ini) and Amiga program that uses generated data.
- Fixed E-Matrix 530/Typhoon MK2 RAM mapping. Now all supported memory sizes work and is detected correctly.
- Modularized expansions device handling more, each device now dynamically adds hsync, vsync, interrupt check etc... callbacks when initialized. Report if some expansion device/device combination stopped working.
- Sprite to bitplane collisions didn't set all CLXDAT bits with certain CLXCON combinations (bad early exit optimization added long time ago)
Fixed CPU tester detected differences between UAE and real CPUs. Mainly undocumented/undefined features, 68020+ T0 trace etc..
UAE = emulation bug fixed, not undocumented feature. No UAE = Undocumented CPU feature (that also needed UAE update)
- LINK stacked value is saved before SP is decreased by 4. Only affects pointless LINK A7,#x variant. (All models except 68040)
- CHK.W undefined flags fully emulated.
- DIVU and DIVS divide by zero condition codes are now 100% correct: DIVS always set Z-flag, DIVU sets Z-flag if dividend upper word is zero, N-flag if dividend upper word is negative.
- CPU bug found and emulated, MOVE.W <EA>,-(An) causing address error: stack frame's opcode field contains following instruction's opcode and "IN" (Instruction/Not) field is set to one! ("Not instruction").
- All instruction address errors should be 100% correct now. An contents are updated (or not updated) if -(an) or (an)+. Condition codes are also correct.
- MOVEM to <EA> with zero register mask: possible odd EA does not cause address error exception. (NOTE: MOVEM from <EA> with zero mask does generate address error exception even if mask is zero because MOVEM that reads from memory always does extra word read)
- BSR.B/W stores old PC to stack and decreases SP before checking if PC is odd.
- DBcc and odd offset: Does not generate address error if condition is true. Count does not affect address error. UAE: Address error stacked PC was wrong.
- UAE: MOVE to SR address error fixed.
- Many instructions update condition codes only partially if it generates address error exception. This is now 100% correctly emulated.
- UAE: More compatible CPU mode didn't split CPU read/write access if it would cross memory banks or wrap around (no normal program is supposed to do this but tester does)
- DIVS.W and divide by zero: undefined V flag is "unstable", when same test is repeated (with V having static value before executing DIWS.W), sometimes it is set, sometimes it is cleared after div by zero. This is not emulated (I have no idea why it works this way. So far this is the only instruction that has this kind of really weird behavior. It does sound like CPU forgets to either copy V to some internal state variables or back when DIVS.W generates div by zero)
- UAE: PACK instruction incorrectly used stack byte decrement behavior (-2) when source parameter was A7.
- UAE: UNPK instruction incorrectly used stack byte decrement behavior (-2) when destination parameter was A7.
- ABCD, NBCD and SBCD always clears undefined V flag.
- MOVES An,(An)+ and MOVES An,-(An) stores incremented/decremented An to memory. (Also 68040)
- CHK.W, CHK.L undocumented flags fully emulated.
- CHK2/CMP2: comparison was not correct when lower bound was larger than upper bound (Documented fully in "M68000 Family Programmer's Reference Manual" "Integer Unit Condition Code Computations" table. Other documentation only mentions inaccurate "If Rn<LB or Rn>UB" formula) . Undefined N and V flags emulated (This was really complex..).
- DIVS.L undefined flags are not fully emulated. (Other DIV variants: fully emulated)
- UAE: BSR and JSR address error fix.
- Both T0 and T1 trace bits set (Documented as "undefined/reserved") is same as T1 only set, normal trace mode (also 68040).
- UAE: MOVE to SR is considered change of flow instruction because it does full pipeline reload (T0 trace, also 68040).
- 64-bit MUL.L: Dh is updated before Dl.
- CAS2 updates Dc2 first, 68020/030 updates Dc1 first. (Only makes a difference if Dc1 and Dc2 is same register)
- LINK stacked value is saved after SP was decreased by 4.
- MOVES An,(An)+ and MOVES An,-(An) stores incremented/decremented An to memory (same as 68020/030)
- 64-bit MUL.L: Dl is updated before Dh.
- DIVU.W and DIVS.W: does not modify undefined N and Z flags if overflow. All other CPU models will modify N and Z flags.
- UAE: Missing 68040-only T0 trace trapping instructions emulated (MOVE to USP, MOVEC, CAS, FSAVE, etc..)
- CHK2/CMP2 undefined N and V flags emulated (Very simple: N is set if source value is negative, V is always zeroed)
- STOP parameter can have S-bit zeroed without privilege violation exception. Only 68060 requires parameter's S-bit being set.
- DBcc generates address error even if odd branch is not taken. (68000-68030 won't)
- Registers are always original unmodified if address error (jump to odd address) is generated.
- DIV.L divide by zero: C flag is cleared. Other flags are not modified.
- CHK clears N-flag if not exception.
- Unaligned MOVE16 works very strangely, need more testing with different accelerator boards.
- UAE: if DIV.L or MUL.L generated exception (unimplemented or div by zero) and addressing mode was -(an) or (an)+: an was not restored.
- MOVES An,(An)+ and MOVES An,-(An) stores non-modified An to memory.
- UAE: Added "Debug Pipe Control Modes" debug instructions HALT and PULSE: HALT = $4ac8 ("TAS A0") and PULSE = $4acc ("TAS A4"). HALT halts the CPU (requires supervisor mode, privilege violation if not in supervisor mode), PULSE does nothing ("toggle non-pipelined mode" says documentation). Other $4ac8-$4acf ("TAS An") instructions generate normal illegal instruction exception.
- UAE: LPSTOP fixed. First it checks if instruction's second word is correct (0x01c0), if not: F-line. Then it checks for supervisor mode, if not: privilege violation. Order was previously swapped.
- UAE: RTE accepted stack frame type 7 which is 68040 only.
- MOVEC with invalid control register in user mode generates illegal instruction exception. Previous CPU models generate privilege violation exception in this situation.
- 68020+ instructions that have extra opword field with zero bit followed by 3-bit REG (data register 0 to 7) field: If zero bit is set to one, REG field becomes address register field! Unfortunately it also seems to make instruction to return incorrect results, it looks like some internal operations use it as DREG and some as AREG. "Zero" bit appears to be not fully supported A/D select bit. (For example MUL.L, DIV.L, CAS2)
- 68060 + DIV.L with second opword zero bits set to one: some combinations seems to hang the CPU! (Internal divide algoritm stuck in infinite loop?)
I haven't found any differences in condition code undefined behavior between 68020 and 68030.
- UAE: Some branch instructions generated wrong stacked trace exception Instruction Address field. (Was branch target, not address of branch instruction)
- UAE: 68000/010 JSR, BSR and RTS didn't check and generate address error if stack pointer was odd. (RTE and RTR did check it)
- UAE: Partially emulate 68010-only bus/address error stack frame. Bus/address error recovery is not emulated, it would be really complex (it is similar to 68030 MMU bus error retry. Most likely no Amiga (or Atari ST) program has ever required 68010 and expected and handled/emulated address errors. Previously 68000 address error stack frame was created
- UAE: 68010 in non-prefetch mode generated and accepted 68020+ stack frame types 1 and 2. 68010 only supports stack frame types 0 and 8.
- Stack pointer was modified before RTE detected format error (unsupported stack frame id), overwriting part of unsupported stack frame. (as usual, probably no program should care)
- Blizzard 1260: BPKT always hangs the system. Warp Engine: randomly hangs. CSPPC: does not hang.
- Blizzard 1260 (rev 1 68060): RESET instruction resets the system even in user mode! CSPPC, rev 1 68060: generates expected privilege violation exception. I don't see how this can be board specific (CPU interrnally generates RESET signal) so perhaps there are different rev 1 68060s?
- 68040: CHK.L #$40000000,D1 (D1=0) is buggy. Execution continues from PC+8, not PC+6! But for example if constant is #$50000000 or D1 is replaced with D0, it works correctly.
Disassembler updates (CPU tester uses disassembler to calculate instruction's source and target EA and length of instruction)
- FDBcc fixed.
- FTRAPcc support added.
- Some variants of MOVE16 didn't disassemble correctly.
- PACK and UNPK support added.
- MUL.L disassembles as MULS.L or MULU.L
- DIV.L disassembles as DIVS.L, DIVU.L, DIVSL.L or DIVUL.L
- CAS fixed.
- LPSTOP fixed.
Undefined flag status:
ABCD, SBCD, NBCD: complete (implemented 10+ years ago)
CHK2, CMP2: complete
DIVU.W, DIVS.W: complete (overflow and div by zero). Except 68020-68030 DIVS.W div by zero "unstable" V flag.
DIVSL.L DIVUL.L, DIVU.L: complete (overflow and div by zero)
DIVS.L: not fully emulated
- A500 SCSI and IDE controller (LX), IDE only (EC)
- SCSI is true DMA! IDE is usual boring PIO.
- Only supports FFS in RDB. If it is the only RDB installed filesystem... Any other filesystem installed: all filesystems gets skipped!
Archos Overdrive HD:
- PCMCIA IDE controller, PIO.
- PCMCIA card appears as a read-only SRAM disk (CC0:, including startup-sequence and everything), data is stored in onboard 32k boot ROM, which loads the IDE driver, mounts the HD, changes assigns and finally executes HD s/startup-sequence.
- "amiquest.device (IDE 5.0 10/02/94)"
- NC53F94 based SCSI controller for M-Tec T1230 A1200 accelerator.
- Fake DMA (long word data port)
- E-Matrix 530 and Typhoon MK2 has same (or almost same) hardware. Driver is also almost identical.
- Emulated as a separate expansion board (not CPU board) because logically it is standard Z2 autoconfig board and it does not depend on accelerator board features in any way and boot rom is located on Mastercard expansion board. Main accelerator board does not have boot rom.
Modificato il 08/09/2019 alle ore 20:46:52
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